Roadmap


2007 to 2013

Core IP developed and patented

•    ReRAM building blocks in place

•    Proof of concept in affordable geometries - basic memory cell works well

•    Patented Interface Switching ReRAM memory cell based on oxygen vacancies


2014

Strategic Partnership Established

•    Joint Development Agreement established with HGST, a Western Digital subsidiary

•    Enables scaling to the geometries that matter for high-density Storage Class Memory

•    Enables 4DS to prove the value of its IP in a cost-effective way


2015

Scalable ReRAM cells developed

•    Public Offer closes oversubscribed

•    Developed functional cells smaller than 250nm with high yield and lot-to-lot consistency

•    JDA with HGST renewed in July 2015

•    A$2.75 million raised


2016

ReRAM cells scaled to 40nm

•    Demonstrated scalability to 40nm which is essential for high-density Storage Class Memory

•    JDA with HGST renewed in July 2016

•    Successfully met the endurance milestone as defined under the 2015 prospectus 

•    A$4.0 million raised 


2017

Speed breakthrough

•    Achieved DRAM-like read speed without the need for speed-crippling error correction

•    JDA with HGST renewed in July 2017

•    Entered into a collaboration agreement with imec 

•    A$3.45 million raised 

Next Steps – Demonstrate a megabit memory in a production-compatible process

•    Develop a production-compatible process for the 4DS Interface Switching ReRAM technology in collaboration with imec using the same state-of-the-art process equipment currently in use by high-density high-volume memory makers.

•    Demonstrate this production-compatible process with imec’s proven memory platform to build a 4DS megabit memory.

•    Collect statistical significant data for yield, speed, endurance and retention at the megabit chip level that high-density high-volume memory makers & buyers need know to make informed decisions.